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2009-04-06 User-customizable verification module to debut
Aegis Software is set launch the third major release of its Version 7 manufacturing operations software, known as R3, at the 2009 APEX exhibition in Las Vegas.
2003-12-20 TINIm390 verification module chipset reference design
This application note provides a technical description of the TINIm390 verification module.
2003-09-19 Getting Started with the TINIm400 (DS80C400) Verification Module
This application note guides users through the initial setup process for the TINIm400 Verification Module.
2002-12-11 Getting Started with the TINIm390 Verification Module
This application note describes the necessary steps to begin development with the Tiny InterNet Interfaces (TINI) Platform.
2003-07-30 Verplex upgrades formal-verification line
On the verge of closing its sale to Cadence, Verplex is releasing an upgrade to its Conformal line of equivalence checkers.
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort
2007-01-31 Verification box exceeds 200MHz speeds
Gidel Ltd's Proc_SoC verification box claims to exceed verification speeds of 200MHz, thanks to a direct FPGA-to-FPGA interconnect scheme
2007-03-16 Take distinctive approach to IC verification
Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification
2006-02-21 Sirit introduces RFID reader module
Sirit introduced a high-frequency 13.56MHz reader module designed for use in cashless payments, secure transactions, access control, identify or product verification and item level tracking in supply chain apps.
2008-02-28 S2C equips Virtex logic module with USB-enabled runtime control
S2C has released its third-generation rapid SoC prototyping tool, the Dual Virtex-5 TAI Logic Module equipped with two Xilinx LX series Virtex-5 FPGAs, which supplies up to 6.6 million ASIC gates of capacity
2008-02-26 Rhines on EDA: End 'endless verification
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification
2002-11-18 Plugging the verification time sink
Logic equivalence checking provides an independent means of verifying the design process and reduces the overall verification effort
2008-03-19 Perform smart verification of GAN-enabled phones
Mobile phone developers have several opportunities to test their GAN implementations against standards. Early verification of a phone's ability to handle data and voice improves the probability of success during conformance testing
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2007-09-21 NI upgrades Vision Development Module for machine designers
NI has announced the newest version of the NI Vision Development Module, a comprehensive library of image processing and machine vision functions for multiple programming languages
2008-02-07 Module measures high-speed serial bus signals
Agilent Technologies has introduced a precision waveform analyzer designed for verification and validation of high-speed electrical communications systems
2005-10-04 Italian SoC design provider offers new mixed-signal verification kit
Yogitech introduced an integrated, automated verification component kit that the company claims goes beyond the limits of traditional mixed-signal verification solutions to drastically reduce verification time and increase quality
2007-09-17 Formal verification fetches better results
Complete formal verification is not a silver bullet for all functional verification tasks. But for a broad range of digital modules and IP, it delivers far superior results in terms of verification quality, effort and costs
2006-12-20 eInfochips verification component supports Mentor's Questa
A component that provides building blocks for efficient design-under-test in module and system-level verification for Mentor Graphics' Questa Vanguard program, including assertion testing, is now available from eInfochips Inc.
2007-06-08 EDA platform offers faster RF module design, verification
Agilent now offers an EDA platform that provides a speedier design and verification process
2005-04-01 China beating U.S. in verification
There is an old expression that says 'the grass is always greener on the other side.' This is a feeling that has existed for a long time between the hardware and software communities.
2015-07-16 Checks for cache-coherency verification in complex SoCs
Coherency seeks to make the caches of a shared-memory system functionally available to all the processors. In this article, we present the efficient checks for cache coherency verification in complex SoCs
2004-10-25 Cadence releases next-gen HW-based verification system
Cadence Design Systems Inc. released its Palladium II system, an integral part of the company's Incisive functional verification platform
2006-06-01 Breaking the verification barrier
Startup OneSpin Solutions believes it has technology that will usher in a new era of IC formal verification. But if this company is successful, the real breakthrough may be one of bringing internal technology from a large integrated device manufacturer into a global, commercial EDA market
2010-08-25 AUO verifies PV module's carbon footprint
Raw materials make up 82 percent of EcoDuo PM220P00's carbon footprint
2010-02-19 Address car hardware, software issues through verification
Many problems occur when hardware meets software, especially in automotive applications. This is where advanced, functional verification methodologies from the hardware world can be very useful
2015-12-22 Accelerate compile/verification under Synopsys VCS
Compilation time can be methodically controlled using a tool developed by Synopsys, the Verilog Compiler and Simulator that uses the Pre-Compilation IP technique.
2008-08-20 3D EM simulation solution rolls for RF module design
Agilent Technologies Inc. has developed the EMDS-for-ADS, an integrated design flow solution that includes full 3D electromagnetic (EM) simulation for RF Module Design
2008-01-15 Test platform supports DSL triple-play service verification
EXFO Electro-Optical Engineering introduces a copper test module for the AXS-200 SharpTESTER platform, which tests the full 30MHz VDSL2 spectrum over copper access networks
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