Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > verilog 4

verilog 4 Search results

?
?
total search110 articles
2005-01-25 Tharas announces support for Verilog 4-state logic simulation
Tharas Systems announced its support for Verilog 4-state logic simulation in its Hammer 100.
2006-03-16 Xilinx releases Virtex-4 FPGA based DDR2 reference design
Xilinx announced the immediate availability of the Virtex-4 FPGA based 667Mbps DDR2 reference design delivering high bandwidth and reliable memory interface solution
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories.
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2010-08-18 Upgraded design suite provides Verilog visualization
Lattice Semiconductor releases Version 1.4 of its ispLEVER Classic design tool suite, which now includes Synopsys Synplify Pro with the HDL Analyst feature set and an ispMACH 4000ZE CPLD fitter
2004-10-13 Mentor tool suite offers complete implementation of Verilog 2001
Mentor disclosed that they have made key enhancements in its newly-released Precision Synthesis tool suite.
2014-06-05 Accellera updates Verilog-AMS with verification, modelling
The enhanced features of Verilog-AMS 2.4 include supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules.
2014-02-10 Performing math operations in FPGAs (Part 4
This instalment focuses on fixed-point representations of numbers.
2006-02-06 Xilinx announces new DDR2 reference design
Xilinx's DDR2-SDRAM interface uses the Virtex-4 ChipSync technology, a run-time calibration circuit that improves design margins and overall system reliability while reducing design cycles
2007-02-01 Video processors roll for mobile handsets, PMPs
Claiming to have solved one of the "grand challenges" of video system design, Tensilica Inc. has introduced a family of software-based video processor engines for mobile handsets and personal media players.
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2003-02-04 Tharas offers 'farm' accelerator license
The company has released a licensing option that allows fuller utilization of its Hammer simulation accelerators.
2004-09-17 Synplicity upgrades FPGA logic, physical synthesis tools
Synplicity announced the latest version of its FPGA logic synthesis and physical synthesis software solutions.
2005-01-03 Startup promises clean RTL code
Stelar Tools claims that its first product will cut 30 percent off the time it takes to move a design from initial RTL code development to synthesis.
2001-04-15 Speed enhancements for Model Tech upgrades
This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support.
2004-06-30 Safelogic rolls out new property checking solution
Safelogic announced a major new release of its property checking solution and extended simulator support for its simulator plug-in product.
2002-05-30 Real Intent brings clock checking to formal tool
Real Intent Corp. has added what it terms formal clock intent verification to its Verix assertion-driven formal verification tool.
2001-05-01 Programmable system chips move forward
Using dedicated hardware to boost real-time performance of embedded systems is a common practice and, with the introduction of PSCs, software engineers will learn how to boost performance of timing-critical software functions.
2002-09-20 Open-source tool offers HDL translation
An open-source tool created by the director of a small silicon IP company translates a subset of RTL VHDL into Verilog
2004-02-16 Mentor Graphics reinforces verification platform scalability
Mentor Graphics has released its ADMS v4.0 with added language support for mixed-signal functional verification.
2003-04-30 Magma folds synthesis into integrated tool suite
Magma Design Automation has unveiled the Blast Create, a single tool that combines silicon virtual prototyping, RTL, and analysis.
2006-07-26 Formal verification tool promises finer control
Averant released the next generation of its formal verification tool, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness.
2015-09-08 Examining performance in hardware emulators
Emulation performanceor the speed of its executiondepends on the architecture of the emulation system and the type of deployment.
2007-01-24 Emulator handles 100 million gates at 20MHz
EVE SA has developed what it touts as the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz, and it supports both hardware and software verification.
2002-02-11 Cynergy closure casts shadow on C design market
Cynergy System Design, a provider of C language design tools, has run out of cash and is closing its doors, according to a former executive.
2016-02-29 Comparison of CPLD-based power mgmt architectures
Know the different sets of compromises and design trade-offs of today's hardware/power management architectures in terms of scalability, design effort and/ cost.
2005-06-13 Celoxica ESL design suite upgrade expands speed, size limits
Celoxica's DK Design Suite introduces VHDL and Verilog optimizations that work with Design Compiler from Synopsys Inc
2006-09-18 Averant dives deep into formal verification
Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top