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2005-01-25 Tharas announces support for Verilog 4-state logic simulation
Tharas Systems announced its support for Verilog 4-state logic simulation in its Hammer 100.
2003-05-02 Speeding up simulation
The paper presented by Rajesh Bawankule at the recent DVCon can help engineers to speed up verilog without spending a single penny
2006-10-17 Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software
2007-06-01 XA offers better simulation accuracy
Promising a new approach to fast Spice simulation, Synopsys Inc. introduced Discovery AMS 2007, a group of solutions that includes the XA simulation technology option for the NanoSim and HSim fast SPICE simulators
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories.
2003-05-29 Verilog simulator supports 64-bit Linux
Claiming a new level of performance, Fintronic USA has announced that its Super FinSim Verilog simulator now runs on 64-bit Linux workstations
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms
1999-10-01 Using parallel-distributed HDL simulation
Parallel-distributed simulations can reduce the time required to perform HDL simulations without dramatically affecting existing design flows. While the theoretical limit of parallel simulations is not reached, the simulation times do approach the limit within reason
2002-02-28 Synopsys Verilog, VHDL simulator improves performance
The company has announced the release of the VCS 6.1 Verilog simulator and the Scirocco 2001.10 VHDL simulator, which are claimed to improve RTL and gate-level simulation performance by up to three times over previous versions.
2006-01-11 SMIC adopts Mentor simulation tool
Semiconductor Mfg Int. Corp. has adopted Mentor Graphics' Eldo simulation tool as an internal SPICE simulator for analog circuits
2002-10-18 Open-source tool links Verilog with TCL
An open-source tool developed by Acculent Corp. promises to convert TCL scripts into Verilog code
2002-06-24 Model simulation tool offers faster performance
Model Technology Inc. has upgraded its ModelSim simulation tool with the release of ModelSim 5.6 that performs simulation at twice the speed of other tools
2004-10-13 Mentor tool suite offers complete implementation of Verilog 2001
Mentor disclosed that they have made key enhancements in its newly-released Precision Synthesis tool suite.
2006-07-14 Mentor integrates fast-SPICE with simulation platform
Mentor Graphics announced the integration of the fast-SPICE simulation technology with its mixed-signal simulation platform, ADVance MS
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications
2002-08-01 Endeavor delivers co-simulation solution for Virtex-II Pro
Endeavor Intertech Corp.'s CoSimple hardware/software co-simulating solution targets Xilinx's Virtex-II Pro FPGAs with the IBM PowerPC 405 processor core.
2012-12-24 Easing system simulation with hardware models
Hardware models can accelerate integration and system verification tasksif they are available early enough in the design flow.
2003-06-10 Dolphin, RidgeTop enhance multi-domain simulation
Dolphin Integration announced a multi-domain simulation flow aimed at accelerating mixed-signal SoC including RF components at the 2003 Design Automation Conference
2000-06-29 Chip-level HDL simulation using the Xilinx Alliance series
This application note describes the basic flow and some of the issues to be aware of for HDL simulation with Alliance Series software. It also familiarizes the user with some of the concepts but should not be considered a replacement for the Xilinx or HDL simulator's documentation
2002-01-16 Assertion methodologies for Verilog design
This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL
2003-10-21 Aldec upgrades dual language simulation environment
Aldec has unveiled a new version of its Riviera dual language simulation environment featuring a two-fold performance increase over the previous version
2006-03-31 Aldec offers 90-day free access to Riviera Verilog simulator
Aldec announced full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems
2003-07-28 Agilent taps startup's Verilog-A compiler
Adding behavioral modeling to its analog design tool suites, Agilent announced an agreement to integrate Verilog-A modeling technology from Tiburon-DA
2004-01-08 Agilent adds Verilog-A support
Claiming a significant advantage over proprietary models, Agilent Technologies has introduced Verilog-A support for its RF Design Environment
2014-11-18 Addressing the problem of X unknowns in simulation
The sheer complexity and common use of power management schemes raise the probability of an unknown X state in the design, translating into a functional bug in the final chip.
2004-06-10 Silvaco rollout includes mixed-signal simulation
During the Design Automation Conference, Silvaco will bring a new mixed-signal simulator, a full-chip RC extractor, a harmonic-balance simulator, an inductance extractor and a soft-error modeling tool.
2004-08-02 Mixed-signal simulation tool supports Linux
Silvaco's mixed-signal simulator, RC inductance extractor and soft-error modeling tool all support Linux under a new GUI.
2003-08-11 TransChip adopts Nassda simulator
TransChip has selected Nassda's HSIM hierarchical circuit simulator and analysis tool for verification of its CMOS imager-based camera-on-a-chip design.
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