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What is Verilog?
The Verilog HDL is an industry-accepted standard hardware description language commonly used to design ASICs and FPGAs. The designers of Verilog wanted to design a language based on the C programming language so that it would be familiar to engineers and readily accepted. In practice, it bears only a vague resemblance to C.
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2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective.
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories.
2003-09-09 Verilog won't diverge, user reps pledge
Although the IEEE and the Accellera standards organization appear to be heading in different directions with next-gen Verilog, IEEE 1364 Working Group and Accellera's SystemVerilog committee members said they won't allow incompatible standards to emerge.
2003-05-29 Verilog simulator supports 64-bit Linux
Claiming a new level of performance, Fintronic USA has announced that its Super FinSim Verilog simulator now runs on 64-bit Linux workstations.
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2004-03-23 Verilog reader/writer boosts OpenAccess reach
Plugging a major gap that has made it difficult for chip designers and EDA vendors to embrace the OpenAccess database, Hewlett-Packard, and Cadence Design Systems have donated a Verilog reader/writer to the OpenAccess Coalition.
2010-08-18 Upgraded design suite provides Verilog visualization
Lattice Semiconductor releases Version 1.4 of its ispLEVER Classic design tool suite, which now includes Synopsys Synplify Pro with the HDL Analyst feature set and an ispMACH 4000ZE CPLD fitter.
2004-06-16 The C programmer's guide to Verilog
This will look at how to implement PWM in software and then turn the design into a logic block that can run from an FPGA and be controlled via software using a memory-mapped I/O interface.
2005-01-25 Tharas announces support for Verilog 4-state logic simulation
Tharas Systems announced its support for Verilog 4-state logic simulation in its Hammer 100.
2003-04-14 Tenison Verilog solution selected by Seaway
Tenison EDA announced that fabless semicon company Seaway Networks Inc. has adopted its Verilog/VHDL to C/C++ modeling solution.
2002-02-28 Synopsys Verilog, VHDL simulator improves performance
The company has announced the release of the VCS 6.1 Verilog simulator and the Scirocco 2001.10 VHDL simulator, which are claimed to improve RTL and gate-level simulation performance by up to three times over previous versions.
2002-09-23 Startup to offer online Verilog training sessions
Mindbrook Inc. will initiate an online Verilog training program that offers software design collaboration in 1H of 2003.
2004-03-05 Silvaco offers open-source Verilog-A models
Silvaco International is offering nine Verilog-A device models for free download under open-source distribution.
2003-06-02 Ready for the Verilog split?
Richard Goering agrees with Cadence that incompatibility between System Verilog 3.1 and IEEE 1364 standard verilog is possible.
2002-10-18 Open-source tool links Verilog with TCL
An open-source tool developed by Acculent Corp. promises to convert TCL scripts into Verilog code.
2004-10-13 Mentor tool suite offers complete implementation of Verilog 2001
Mentor disclosed that they have made key enhancements in its newly-released Precision Synthesis tool suite.
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications.
2004-06-29 IEEE unifies Verilog standards efforts
Putting to rest fears of a Verilog language schism, the IEEE has decided to form a single working group that will encompass both SystemVerilog and the further evolution of the IEEE 1364 Verilog language standard.
2004-01-05 EDA startup offers graphical Verilog tool
Aiming to simplify HDL code development and documentation, Orion Consulting Inc. has rolled out Visual RTL.
2003-04-09 Cadence decries incompatible Verilog versions
The EDA industry is risking "disaster" with two separate and incompatible versions of Verilog unless the Accellera standards organization quickly hands over SystemVerilog 3.1 to the IEEE, according to Cadence Design Systems Inc.
2002-01-16 Assertion methodologies for Verilog design
This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL.
2006-03-31 Aldec offers 90-day free access to Riviera Verilog simulator
Aldec announced full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.
2006-10-17 Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software.
2003-07-28 Agilent taps startup's Verilog-A compiler
Adding behavioral modeling to its analog design tool suites, Agilent announced an agreement to integrate Verilog-A modeling technology from Tiburon-DA.
2004-01-08 Agilent adds Verilog-A support
Claiming a significant advantage over proprietary models, Agilent Technologies has introduced Verilog-A support for its RF Design Environment.
2014-06-05 Accellera updates Verilog-AMS with verification, modelling
The enhanced features of Verilog-AMS 2.4 include supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules.
2004-01-16 'Obfuscators' render Verilog, VHDL unreadable
Providing a new approach to IP protection, software engineering firm Semantic Designs has released production-quality "obfuscators" for Verilog 2001 and VHDL.
2006-10-04 Yogitech unveils 'first' Open Core Protocol UVC
Yogitech, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol universal verification component.
2004-02-02 Write your own PCB design rule checker
After PCB design is captured in a schematic tool, a design rule checker (DRC) must be run to find any design rule violations. This must be done before backend processing starts.
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