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What is VHDL?
VHSIC Hardware Description Language (VHDL), where VHSIC is an acronym for Very High-Speed Integrated Circuits. It's an IEEE-standard HDL that was originally developed by the U.S. department of defence for documenting electronic systems. The language is specified in the IEEE 1076 standard and used to describe and simulate ICs and systems before fabrication. It is an alternative language to Verilog.
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2006-04-28 VDA VHDL-AMS models run in Synopsys' simulator
Synopsys announced that it has qualified the VHDL-AMS models to run in the Synopsys Saber simulator for use by automotive OEMs and suppliers.
2001-03-22 Using hierarchy in VHDL design
This application note describes VHDL's features, which are specifically designed to make hierarchical design both simple and powerful, and presents a simple example of how these features might be used.
2002-02-28 Synopsys Verilog, VHDL simulator improves performance
The company has announced the release of the VCS 6.1 Verilog simulator and the Scirocco 2001.10 VHDL simulator, which are claimed to improve RTL and gate-level simulation performance by up to three times over previous versions.
2003-04-15 Synopsys executive predicts end of VHDL
Synopsys' chairman and CEO Aart de Geus predicted that VHDL will go away in 10 years. De Geus made his prediction at the Synopsys Developers Forum in Santa Clara, California.
2003-04-08 Safelogic VHDL tool sweetened with Sugar
Safelogic Verifier 3.1 product now supports PSL.
2006-11-16 Revised VHDL boosts IP security
The Accellera standards organization has approved a revised version of the VHDL specification, marking a huge step forward for the design language.
2006-10-10 Revised VHDL adds IP encryption capability
Proclaiming a major step forward for the VHDL design language, the Accellera standards organization this week announced it has approved a revised version of the VHDL specification, which features Property Specification Language (PSL) assertions and IP encryption capabilities.
2002-10-11 ispLSI 8000V Family VHDL Code Examples
This application note talks about the ispLSI8000V family architecture features and includes coding examples designed to allow the user to take advantage of its hardware capabilities.
2001-03-20 Getting started converting .ABL files to VHDL
This application note is intended to assist Warp users in converting designs written in DATA I/O's ABEL 7 HDL to IEEE 1076 VHDL.
2001-03-21 FIFO Dipstick using Warp2 VHDL and the CY7C371
This application note presents a method by which FIFOs of any size may be monitored by an external PLD that will then generate all of the flags necessary for most FIFO applications.
2001-03-19 Designing with the CY7C335 and Warp2 VHDL compiler
This application note provides an overview of the CY7C335 Universal Synchronous EPLD architecture and Warp2 VHDL Compiler for PLDs.
2005-02-25 C/C++ to VHDL for $995
Orange Tree Technologies and SystemCrafter announce the SystemCrafter package for SystemC development work.
2008-04-09 ANSI-C to VHDL compiler tailored for FPGA designs
Paolo Palazzari, the Ylichron CTO for software activities, announced the availability of what he claims to be the first true ANSI-C to VHDL compiler targeting the FPGA market.
2006-07-26 Accellera approves new VHDL standard
Accellera announced that its members approved a new VHDL standard, a VHDL Applications Programming Interface (API) known as VHPI on June 28.
2001-03-20 Abel-HDL vs. IEEE-1076 VHDL
This application note compares and contrasts the complexity and basic features of Abel-HDL with those of IEEE-1076 VHDL.
2004-01-16 'Obfuscators' render Verilog, VHDL unreadable
Providing a new approach to IP protection, software engineering firm Semantic Designs has released production-quality "obfuscators" for Verilog 2001 and VHDL.
2006-10-04 Yogitech unveils 'first' Open Core Protocol UVC
Yogitech, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol universal verification component.
2004-03-25 Verisity adds accelerators, emulators to Axis line
Verisity Ltd plans to add dynamically programmable processors to the XoC, Xtreme, and Xcite acceleration and emulation products it acquired in the deal last month for Axis Systems Inc.
2001-04-15 Verification firm starts partners program
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry.
1999-10-01 Using parallel-distributed HDL simulation
Parallel-distributed simulations can reduce the time required to perform HDL simulations without dramatically affecting existing design flows. While the theoretical limit of parallel simulations is not reached, the simulation times do approach the limit within reason.
2003-08-01 Using FPGAs for measurement, control
Find out the benefits and challenges of using FPGAs in systems that require measurement and control functionality.
2008-09-16 Two-dimensional rank order filter
This application note describes the implementation of a two-dimensional Rank Order filter. The reference design includes the RTL VHDL implementation of an efficient sorting algorithm.
2003-11-25 Translogic HDL Companion targets complex designs
Translogic BV has announced that it has made its HDL Companion 1.0 available for free evaluation.
2003-07-09 Toshiba uses Tharas devices on verification flow
Toshiba Corp. has selected Tharas Systems' Hammer systems and the Hammer Accelerator Farm to be deployed into its DFT verification flow.
2005-07-01 Tips for compiling software to gates
VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages
2001-03-19 The FLASH370i family of CPLDs and designing with Warp2
This application note covers the following topics: a general discussion of complex programmable logic devices (CPLDs); an overview of the FLASH370i family of CPLDs; and using the Warp2 VHDL Compiler for the FLASH370i family.
2000-12-01 The advantage of using logic BIST for ASIC designs
This technical paper reveals the advantage of using logic BIST for ASIC designs.
2004-05-13 Tharas spins new accelerator box
Tharas' new version of its hardware accelerator compiles Verilog, VHDL or mixed-language designs at rates of 20 to 50 million register-transfer-level equivalent gates per hour.
2003-04-14 Tenison Verilog solution selected by Seaway
Tenison EDA announced that fabless semicon company Seaway Networks Inc. has adopted its Verilog/VHDL to C/C++ modeling solution.
2005-06-16 SystemVerilog enhances assertion-based verification
ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how
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