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2005-08-16 Tool gets a handle on voltage changes
As a chip designer for Intel Corp., Srikanth Jadcherla spent a lot of time working on multivoltage designs. Now he's launched an EDA startup, ArchPro Design Automation Inc., which is rolling out what it presents as the industry's first multivoltage RTL simulation product.
2002-02-12 Scaling debate stalks chip conference
From the wide range of panels and tutorials at the International Solid-State Circuits Conference, from the myriad papers, from the conversations in the hotel halls, a single gnawing issue grew from hints and whispers to a groundswell of concern: Will IC technology continue to scale?
2008-04-16 Scale voltage to manage power consumption
As CMOS process technologies migrate from 90nm to 65nm and below and as chip densities increase, static and dynamic power consumption often rise above acceptable levels. Apply voltage-scaling techniques to manage both.
2005-06-10 Power conservation options with dynamic voltage scaling in portable DSP designs
This app note demonstrates power conversion options with dynamic voltage scaling in portable DSP designs.
2006-06-13 DC/DC converters ease digital voltage scaling
Texas Instruments' two new dual-output, step-down DC/DC converters with a unique one-pin serial interface promise simple digital voltage scaling.
2014-06-25 Adaptive voltage scaling boosts energy efficiency
Adaptive voltage scaling is a powerful technique that optimises supply voltages and minimises energy consumption by modern high-performance microprocessors.
2015-03-31 Voltage monitors draw 6?A quiescent current
Linear Technology bared its single/dual channel LTC2965 and LTC2966 low-dropout regulators that feature wide operating range, low power consumption and accurate monitoring.
2016-04-11 Probing ReRAMs: Forming scaling, quantised conductance
Learn about the new ReRAM challenges as an IMEC team have formed and characterised the electrical conductance and topology of some of the smallest ReRAM filaments ever reported.
2012-02-23 PCM progress report no. 5: Scaling issues
Learn about the possible approaches to achieve the scaling necessary to make PCM a commercial success
2013-07-05 NAND flash scaling: 20nm node and below
Here are some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology.
2012-02-24 Integrated voltage regulators cut power by 20
Inverted voltage regulation will be able to respond to the energy needs of future CMOS chips in nanoseconds, compared to microseconds with off-chip voltage regulators, the researchers said
2015-04-13 High-voltage IC technology for bias supply design
Here's a look at some of the key requirements and challenges in designing off-line, non-isolated bias supplies, and how high-voltage IC technology can help simplify such designs
2009-02-12 Five ways to beat IC scaling roadblocks
Intel senior fellow and director of process architecture Mark Bohr listed five major stumbling blocksor challengesfor the 32nm node and beyond.
2007-08-01 Employ supply voltage control to save energy
Combining dynamic voltage and frequency scaling with power gating can reduce energy consumption in circuit operations to help prolong battery life in mobile devices.
2006-08-16 CMOS scaling: painstaking but possible
CMOS scaling is, in fact, proving to be a painstaking and humbling taskalbeit a possible one
2011-10-14 Buck regulators tout 4.5-16V input voltage range
Summit's 10A and 20A DC/DC products have built-in MOSFETs and claim to deliver 96 percent efficiency.
2012-02-27 Buck regulators offer 4.5-16V input voltage range
The SMB206A and SMB210A are dual 3A and single 6A programmable integrated DC/DC regulators with switching frequency programmable to 500kHz or 1MHz.
2012-05-30 ARM CTO calls for architecture scaling for 2020 soln's
Major advances have been made regarding systems, hardware, operating systems and applications but Muller outlined the needs of architecture scaling for 2020 solutions
2015-02-27 ADI touts user-programmable voltage output DAC
The AD5761R integrates a 16bit data converter, 2ppm/C 2.5V reference, output buffer and gain scaling function on-chip, allowing for faster and simpler system design
2013-07-08 Addressing memory scaling concerns
Here are some promising research and design directions to overcome challenges posed by memory scaling
2010-03-26 25nm MLC NAND breaks scaling barriers
While most pundits have speculated that NAND has hit the wall, IM Flash Technologies continued their aggressive path scaling with the 25nm 8Gbyte, 2bit/cell MLC NAND
2007-08-16 Off-chip ESD protection anticipates IC scaling
Tomorrow's electronic products need more robust off-chip ESD protection to provide the current level of system protection. By selecting a protection TVS with good clamping performance and applying some basic layout techniques, designers can maximize the chance of passing ESD testing the first time at the compliance lab and ensure greater product reliability in the field.
2002-06-19 Materials transitions stalk CMOS scaling
With the transition to copper and low-k interconnects showing just how difficult changes in materials can be, technologists gathered at the Symposium on VLSI Technology to consider a brace of materials challenges?ranging from new gate oxides to SOI and strained-silicon channels.
2012-08-15 Optimize dynamic power signature of digital ICs to reduce power noise
At advanced process nodes, the biggest hurdle to achieving power noise integrity lies in handling high frequency power demand.
2008-03-07 LDOs consume 'lowest' quiescent current at 500nA
TI has introduced a family of LDOs with dual-level voltage output that consume the lowest quiescent current in the industry at 500nA
2008-08-04 LDO regulators eye high efficiency applications
Micrel Inc. introduces the MIC5313/4/5/6, a new family of low input voltage capable, low dropout (LDO) regulators
2012-11-12 Integrated power IC ready for Quad-core apps processors
Dialog's DA9063 can deliver up to 12A from its six DC/DC converters, 24% more than its nearest rivals.
2013-04-02 FinFETs still not ready for prime time
Rising capacitance is one of many challenges that lie ahead before a process node that utilises 3D transistors can be realised, according to a panel of experts at the annual Synopsys User Group meeting.
2007-10-16 Dual-level LDO simplifies programming of eFUSE, SIM cards
TI has introduced a dual-level 200mA LDO linear regulator with simple dynamic voltage scaling in a tiny, five-ball chip-scale package, a first of its kind according to the company.
2007-12-03 Achieve processor energy savings with AVS
Processing large amounts of data at fast speeds rapidly drains the power of a mobile device battery. Maximizing energy savings can be achieved with an AVS technique to reduce energy consumption in digital processors by up to 70 percent.
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