Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > wafer level packaging

wafer level packaging Search results

?
?
total search296 articles
2008-11-21 Wafer-level packaging achieves prominence
Wafer-level packaging, the fabrication of the IC package directly on the wafer, is finally getting exposure after many years of promises, according to an expert in the field.
2009-04-02 Wafer-level optics tech licensed to Qtech
Q Technology Ltd has licensed Tessera Technologies Inc.'s OptiML wafer-level optics (WLO) technology for next-generation mobile electronics. China-based Qtech will integrate the technology into its compact modules for cellphone and notebook computer applications
2011-11-22 Wafer packaging fab opens in Taiwan
STATS ChipPAC has increased production capacity with the completion of its 300mm wafer bump and WLCSP facility
2003-09-22 Wafer bumping technology qualified at Chartered
Unitive Semiconductor Taiwan Corp. (UST) has announced that its electroplated wafer bumping technology has been qualified at Chartered Semiconductor
2002-07-05 Unitive adopts Semitool's packaging platform
Semitool Inc. has announced the delivery of its electroplating system product, the Advanced Packaging Platform (APx), to Unitive Inc
2008-06-20 Unisem, FlipChip deal zeroes in on wafer technologies
Unisem and its subsidiary Unisem-Advanpack Technologies Sdn Bhd (UAT) have entered into an agreement with FlipChip International LLC (FCI) for the licensing of FCI's wafer bumping and wafer level packaging technologies.
2011-04-11 TSMC enters chip-packaging arena
TSMC will soon open a bumping facility and offer silicon interposers and TSV technologies for 3D chips, but will remain focused on the foundry market and will not compete against subcontractors.
2008-09-04 Tegal secures products, IP for 3D packaging, MEMS
Tegal Corp. has signed an agreement with AMMS and Alcatel-Lucent to acquire products and the related intellectual property, directed at advanced 3D wafer-level packaging applications.
2014-03-13 STATS ChipPAC unveils novel wafer level manufacturing
FlexLine claims to provide freedom from wafer diameter constraints while enabling supply chain simplification and cost reductions that are not possible with a conventional manufacturing flow
2015-09-28 SiP, PVS tech enabled for TSMC InFO packaging
Cadence said the Allegro SiP design tools and PVS allow TSMC customers to cut the InFO design and verification cycle by offering an integrated solution that automates the design-rule checking (DRC) flow.
2007-08-17 Shifting trends in packaging industry favor big players
Industry insiders agree the packaging business is getting increasingly expensive, a trend that naturally favors larger players
2003-07-07 SECAP installs wafer line at Hsinchu
The Semiconductor Equipment Consortium for Advanced Packaging has installed a 300mm wafer bumping and WLP line at Unitive Semiconductor located in Hsinchu, Taiwan
2015-02-05 Rudolph sends JetStep for fan-out packaging apps
The JetStep Advanced Packaging Lithography System handles both warped wafers and flexible substrates. It offers 52mm x 66mm field view and 30-reticle library
2014-02-07 Rise of mobile devices push market for wafer-level packaging
ReportsnReports predicted that the global wafer-level packaging equipment market will grow at a CAGR of 2.9 percent over the period from 2013-2018.
2013-05-29 Removing field failures at wafer level (Part 1
Here's a look at Sonoscan's new automated wafer inspection system and its advantages
2005-10-21 Packaging conference to explore 3D, SIP
Building on the first International Wafer-Level Packaging Congress (IWLPC) event, the second IWLPC conference will explore three-dimensional (3D) chip-packaging and other technologies.
2015-06-29 OSATS: Wafer-level packaging limitations hard to dismiss
The recent SEMI Packaging Tech Seminar focused on the need, in terms of under yield and packaging cost pressures, to move from fan-out wafer-level-packaging to fan-out panel-level-packaging.
2013-08-14 NTU, STATS ChipPAC work on advanced wafer level packaging
Singapore's NTU has entered a joint research programme with STATS ChipPAC to advance solutions for next generation semiconductor packaging technologies
2006-07-26 New wafer bonding system targets advanced MEMS
Touted to be an industry-first, SUSS MicroTec's field upgradable load locked wafer bonding system was developed for advanced MEMS devices
2013-07-26 Metrology system configured for advanced packaging
Rudolph Technologies' metrology suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3D ICs using through-silicon via (TSV) as interconnects.
2007-11-14 Infineon reveals new packaging technology
Infineon Technologies unveils a new package technology, and has tapped Advanced Semiconductor Engineering as its IC packaging partner
2003-10-22 IMEC, EVG partner on packaging, bonding techniques
Inter-university MicroElectronics Center (IMEC) and EV Group (EVG) have signed a joint development agreement on wafer-level packaging and MEMS wafer bonding.
2007-11-16 Image sensor packaging slims down for CE, cars
Solid-state image sensors must be packaged to protect against corrosion, mechanical damage and obscuration by dust particles. Current wafer-level packages provide a low-cost, chip-size solution with a total thickness of less than 500m that will also pass stringent automotive reliability standards
2007-09-12 Firms form forum to promote wafer-level CSP
Major industry firms have joined hands and formed the WLCSP Forum to promote the adoption of semiconductor devices using wafer-level CSP
2015-02-26 Fan-out wafer level packaging to reach $200 million, analysts say
Market researchers predict in a new report that the Fan-Out Wafer Level Packaging (FOWLP) market is likely to reach an estimated $200 million in 2015, expects 30 per cent CAGR in the following years.
2007-10-25 EDA's big three unready for 3D chip packaging
Without design tools to allow exploration and tradeoffs to be made in 3D layouts, engineers are restricted to design in two dimensions and occasionally stack chips crudely. But without a clear market for 3D design EDA vendors are unlikely to offer tools.
2005-01-20 Casio licenses packaging technology to Renesas
Casio Computer Co. Ltd has licensed its wafer level packaging (WLP) technology to Renesas Technology Corp. in an attempt to create an industry de facto packaging standard.
2005-05-03 ASE, FCI ink wafer level packaging deal
Advanced Semiconductor Engineering Inc. (ASE) and FlipChip International LLC (FCI) have signed an expanded technology licensing agreement.
2011-04-18 Applied announces packaging, display forays
Applied Materials has teamed up with IME to build a center for advanced packaging in Singapore
2007-07-19 Amkor, IMEC sign 3D wafer-level packaging pact
Amkor has agreed to develop 3D integration technology with IMEC based on its wafer-level processing techniques
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top