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2012-08-21 Utilize wafer-scale CMOS X-ray imaging for medical apps
This imaging technology can bring key advantages in terms of performance such as high resolution, high dynamic range and low noise capabilities.
2007-07-23 IBM fab starts using Pb-free packaging process
IBM Corp. has started using C4NP, a Pb-free process that reduces the cost of packaging flip-chip devices
2003-01-29 Xanoptix stacks chips to create hybrid ICs
Startup Xanoptix Inc. has developed a wafer-scale manufacturing process that allows silicon die, optical semiconductors, and compound semiconductors such as GaAs and InP chips to be stacked into 3D structures to create hybrid ICs.
2013-10-02 Researchers demonstrate carbon nanotube powered computer
Stanford researchers hope to revitalise carbon-nanotube development efforts by surmounting its problems with a CMOS compatible process they call "imperfection-immune design
2014-04-03 Gpixel endows CMOS image sensor with 150Mpx res
The sensor was developed using TowerJazz's TS18IS manufacturing technology, enabling scaling to 167.6mmx30.1mm die size
2015-06-24 Scalable production of low-temperature 2D MoS2 films
Researchers at the University of Southampton's Zepler Institute characterised large-area 2D films of molybdenum disulphide at room temperature using a process that is scalable to any size wafer
2009-02-03 U.S. Army invests in flexible electronics R&D
The U.S. Army has committed to sponsor an additional five years of R&D at Arizona State University's (ASU) Flexible Display Center.
2015-07-30 Diamond substrate unleashes GaN potential
Diamond substrates and heat spreaders enable GaN devices to operate near its peak power output without degradation in lifetime.
2013-05-15 CTO: TSMC prepared to push beyond IC limits
TSMC technology chief Jack Sun discusses the future of semiconductors-such as super-systems that move beyond SoCs-and the path the microchip foundry aims to take.
2007-08-01 Bosch sees huge potential in tiny MEMS
Bosch sensor engineering VP Horst Mnzel and Bosch Sensortec general manager and CEO Frank Melzer recounted the history of MEMS development at Bosch and shared its plans for the technology in a conversation with EE Times.
2012-04-17 Addressing integration concerns with SiP technologies
Learn about the benefits and drawbacks of system-in-package technologies.
2007-12-17 'Chip-on-MEMS' enables wafer-level calibration
A new technique called "chip-on-MEMS" bonds ASIC dice atop an entire MEMS wafer before dicing, according to developer VTI Technologies.
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