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2000-06-26 XC4000 series technical information
This application note contains additional information that may be of use when designing with XC4000 Series devices. This information supplements the product descriptions and specifications, and is provided for guidance only.
2000-06-21 XC4000 series edge-triggered and dual-port RAM capability
This application note examines the edge-triggered capability of the XC4000 FPGAs to simplify system timing and provide better performance for RAM-based designs. It also discusses these FPGAs' dual-port mode, which offers new capabilities and simplifies FIFO designs.
2000-06-23 Using the XC4000 readback capability
This application note describes the XC4000 readback capability and its use. It discusses initialization of the readback feature, format of the configuration and readback bit streams, timing considerations, software support for reading back LCA devices, and CRC.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-21 Implementing FIFOs in XC4000 series RAM
This application note demonstrates how to use the various RAM modes in XC4000 series logic blocks. A simple FIFO is implemented in several different ways, using combinations of level-sensitive (asynchronous) and edge-triggered (synchronous), single-port and dual-port RAM.
2000-06-27 Design migration from XC4000 to XC5200
This application note reviews the differences between the XC5200 and XC4000 families, recommends approaches for converting XC4000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.
2000-06-26 Design migration from XC4000 to XC4000E
This application note describes techniques that should be employed to convert from any of the XC4000, XC4000A, XC4000D, or XC4000H families to the XC4000E family
2000-06-23 Boundary scan in XC4000 and XC5200 series devices
This application note describes the boundary-scan facilities in the XC4000 and XC5200 Series FPGAs, and explains how boundary scan is incorporated into an FPGA design.
2000-06-22 Accelerating loadable counters in XC4000
This application note describes a technique for increasing the performance of very compact, high-performance counters, which are provided by the XC4000 dedicated carry logic, using minimum additional logic.
2000-06-27 Xilinx FPGAs: A technical overview for the first-time user
This application note introduces the reader to the various Xilinx product families' logic components and provides a general overview of what the logic components within the devices are used for.
2000-06-22 Ultra-fast synchronous counters
This application note discusses the implementation of a fully synchronous, non-loadable, binary counter by using the XC4000 and XC3000 FPGA designs.
2000-06-22 Synchronous and asynchronous FIFO designs
This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000-Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks.
2004-05-06 Nayna rolls first-mile Ethernet access boxes
Nayna Networks will unveil a first-mile Ethernet access box that allows carriers to choose between point-to-point Ethernet and Ethernet PON connections.
1999-10-09 Metastable Recovery
This paper deals with the XC4000 and XC3000-series flip-flops and how they perform well in metastable conditions for MSI and PLDs.
2000-06-26 Harmonic Frequency Synthesizer and FSK Modulator
This application note discusses a harmonic frequency synthesizer, that uses an accumulator technique to generate frequencies that are evenly spaced harmonics of some minimum frequency, and an FSK modulator, which provides a modification of the harmonic frequency synthesizer and automatically switches between two frequencies in accordance with an NRZ input.
2000-06-29 Frequency/Phase comparator for phase-locked loops
This application note describes a phase comparator that permits PLLs to be constructed using LCA devices, which only require an external VCO and integrating amplifier.
2000-06-27 FPGA configuration guidelines
This application note discusses FPGA configuration guidelines that describe the configuration process for all members of the XC2000, XC3000, XC4000 and XC5200 FPGA devices and their derivatives.
2000-06-28 Dynamic reconfiguration
This application note describes the procedures for reconfiguring the more traditional Xilinx FPGAs of the XC3000, XC4000, and XC5200 families.
2000-06-23 Configuring mixed FPGA daisy chains
This application note demonstrates how to configure the XC2000, XC3000, XC4000 and XC5200 FPGAs in a common daisy-chain structure.
2000-06-26 Configuring FPGAs over a processor bus
This application note describes how to configure an FPGA over a processor bus. It also illustrates the source code required to download a configuration bit-stream using an IBM PC as a host microprocessor.
2000-06-28 Configuration issues: Power-up, volatility, security, battery back-up
This application note covers several related configuration subjects including: the power up details of Xilinx FPGAs; Xilinx FPGA reaction to power-supply glitches; danger of picking up erroneous data and configuration; ways to maintain configuration during loss of primary power; and ways to secure a design against illegal reverse engineering.
2000-06-28 Choosing a Xilinx product family
This application note describes the various Xilinx product families. Differences between the families are highlighted. The focus of the discussion is how to choose the appropriate family for a particular application.
2000-06-26 Bus-Structured Serial Input/Output Device
This application note discusses how to implement an extensive bus structure by using simple shift registers to illustrate how 3-state busses may be used within an LCA device.
2000-06-23 Block Adaptive Filter
This application note describes a specific design for implementing a high-speed, full precision, adaptive filter in the XC4000E/EX family of FPGAs.
2000-06-22 16-Tap, 8-Bit FIR filter applications guide
This application note describes the functionality and integration of a 16-tap, 8-bit Finite Impulse Response (FIR) filter macro with predefined coefficients, such as low pass, and a sample rate of 5.44MSa/s or 784 MIPS using an XC4000-4 device.
2012-05-24 Low-power DSP architecture meets wide range of wireless standards
The CEVA-XC4000 programmable low-power DSP architecture framework uses an innovative instruction set to enable highly complex, software-based baseband processing which otherwise could only be accomplished with dedicated hardware.
2012-02-23 DSP cores offer wide compatibility with comms standards
CEVA's XC4000 processors are based on a single, newly designed low-power DSP framework and also maintain backward compatibility with the company's previous communication processors.
2000-06-26 Design of 4Mb Virtual SPROM
This application note describes the design of a very low cost, CPLD-based virtual SPROM for downloading programming information to the Xilinx high-density XC4000 Series FPGAs.
2008-01-09 Xceive eyes for the demise of the CAN tuner
"The end of CAN tuner has begun." So says Xceive Corp., a producer of RF-to-baseband transceivers for the TV, PC and STB markets.
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