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2000-06-27 Xilinx FPGAs: A technical overview for the first-time user
This application note introduces the reader to the various Xilinx product families' logic components and provides a general overview of what the logic components within the devices are used for.
2000-06-21 XC4000 series edge-triggered and dual-port RAM capability
This application note examines the edge-triggered capability of the XC4000 FPGAs to simplify system timing and provide better performance for RAM-based designs. It also discusses these FPGAs' dual-port mode, which offers new capabilities and simplifies FIFO designs.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-26 System design with new XC4000X I/O features
This application note examines the I/O features of the XC4000X FPGA family including an additional latch on each input and an output multiplexer on each output. These features are discussed, and examples show how to use them.
2000-06-22 Synchronous and asynchronous FIFO designs
This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000-Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks.
2000-06-21 Implementing FIFOs in XC4000 series RAM
This application note demonstrates how to use the various RAM modes in XC4000 series logic blocks. A simple FIFO is implemented in several different ways, using combinations of level-sensitive (asynchronous) and edge-triggered (synchronous), single-port and dual-port RAM.
2000-06-20 I/O characteristics of the 'XL FPGAs
This application note describes I/O parameters of the 'XL FPGA family in analog terms, giving the designer a better understanding of the circuit behavior.
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