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XC4000 series edge-triggered and dual-port RAM capability 2000-06-21
This application note examines the edge-triggered capability of the XC4000 FPGAs to simplify system timing and provide better performance for RAM-based designs. It also discusses these FPGAs' dual-port mode, which offers new capabilities and simplifies FIFO designs. ?
Using the ORCA Series 4 EBR as a True Quad-Port RAM 2002-12-11
This application note provides the details required to use the ORCA Series 4 EBR as a true quad-port memory. ?
Using Select-RAM Memory in XC4000 Series FPGAs 2000-06-21
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning. ?
Using Select-RAM Memory in XC4000 Series FPGAs 2000-06-21
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning. ?
Using External RAM with PIC17CXX Devices 2000-06-01
This technical note shows how to connect a PIC17CXX device to external memory. It also provides instructions and calculations to help determine which speeds of SRAM work with which frequency crystal. ?
Using EDAC RAM for RadTolerant RTAX-S/SL and Axcelerator FPGAs 2008-10-06
In space applications, storage elements like SRAMs are susceptible to the impact of heavy ions from cosmic galactic rays. CGRs can collide with the silicon lattice of a RAM cell with sufficient photovoltaic energy to produce a change of state, thus invalidating the stored data and producing bit errors. ?
QuickLogic PolarPro RAM and embedded FIFO controller 2008-10-20
This document outlines QuickLogic PolarPro RAM and FIFO controller features and modes. ?
Interfacing the FLEx72 18Mbit synchronous dual-port RAM to the TI TMS320C641x DSPs 2008-05-22
. This application note describes wiring, EMIF register settings and other design considerations for connecting the TMS320C6416 DSP to the Cypress FLEx72 18Mbit synchronous dual port. ?
Implementing FIFOs in XC4000 series RAM 2000-06-21
This application note demonstrates how to use the various RAM modes in XC4000 series logic blocks. A simple FIFO is implemented in several different ways, using combinations of level-sensitive (asynchronous) and edge-triggered (synchronous), single-port and dual-port RAM. ?
Implementing depth expansion with the Cypress FLEx72 18Mbit dual-port RAM 2008-05-22
This application note discusses the Cypress FLEx72 18Mbit dual-port RAM (CYD18S72V) is the industry's first DP RAM with support for a 72bit wide data bus. ?
Implementing a 128Kx32 dual-port RAM using the FLASH370 2001-03-21
This application note describes how to implement a 128K-by-32-bit-wide dual-port memory or larger, using high-speed 1MB SRAMs and Cypress Semiconductor's CY7C371 CPLD. ?
Design guidelines for microcontrollers incorporating NV RAM 2001-04-11
This application note discusses design guidelines for Dallas Semiconductor's Secure Microcontroller family and DS87C530 High-Speed Microcontroller products that incorporate nonvolatile SRAM. ?
Delta39K and Quantum38K dual-port RAM 2001-03-21
This application note provides information and instruction in implementing synchronous/asynchronous dual-port RAM (DPRAM) in Delta39K and Quantum38K CPLDs. ?
Using the Virtex Block SelectRAM+ 2000-06-23
This application note demonstrates how to utilize the Virtex FPGA Series' dedicated blocks of on-chip 4.096kb dual-port synchronous RAM by using each port of the block SelectRAM+ memory independently as a read/write, read or write port, and configure each port to a specific data width. ?
Using CodeWarrior Linker Command File for Qorivva/PX 2013-08-16
Know the steps to create LCF from scratch and the common as well as unique application requirements handled in LCF. ?
Using CellularRAM memory to replace Fujitsu 3V FCRAM 2009-06-09
This application note addresses requirements for a design migration from 3V FCRAM to CellularRAM devices. It also describes the comparative device overview, interface-change requirements, device driver requirements and added benefits of using CellularRAM memory. ?
Understanding synchronous dual-ports 2001-03-29
This application note explains the basic operations and features of Cypress Semiconductor's synchronous dual-port memories. ?
Understanding asynchronous dual-port RAMs 2001-03-29
This application note examines the evolution of multi-port memories and explains the operation and benefits of Cypress Semiconductor's asynchronous dual-port RAMs. It also explores the benefits of using dual-port RAMs over single-port RAMs in multiprocessor systems. ?
The X24C44 NOVRAM Teams up with 8051 microcontrollers 2003-04-30
This application note describes how to interface the X24C44 with the 8051 family of microcontrollers. ?
Synthesizable 143MHz ZBT SRAM interface 2000-06-23
This application note demonstrates a Virtex design that interfaces to megabytes of external high-speed ZBT (Zero Bus Turnaround) SRAM in order to provide interleaved read/write without wasteful turnaround cycles. ?
Synchronous dual-port static RAMs for DSP and communications applications 1999-10-15
Data transfers are moving towards being more synchronous and may be random, sequential, pipelined, and/or non-pipelined applications. If dual-ported technology is the answer, then synchronous dual-ported SRAM will carry today's designs even further. ?
Synchronous and asynchronous FIFO designs 2000-06-22
This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000-Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. ?
SH7641 MCU: Output of three-phase complementary PWM signals 2007-02-05
This article describes a sample task in which PWM waveforms in three-phases are output along with corresponding inverse waveforms that include non-overlapping sections. ?
Rewriting flash memory in user program mode using asynchronous serial communication 2007-02-05
This article describes how data to be rewritten in the flash memory on the master side is written to the flash memory on the slave side, and how data to be rewritten is transferred using asynchronous serial communication. ?
Performance differences between the MPC8240 and the MPC106 2000-05-16
This paper discusses some of the major performance differences between the MPC8240s memory and PCI interfaces and those of the MPC106. ?
NV SRAM Frequently Asked Questions 2002-11-26
This application note list down the frequently asked questions and the corresponding answers for NV SRAMs. ?
NOVRAM AUTOSTORE Considerations 2003-04-30
This application note lists considerations when using the AUTOSTORE function of the NOVRAM devices. ?
MB86930 SPARClite DRAM CONTROL INTERFACE 1999-12-10
This application note outlines the design used on the Fujitsu SPARClite Evaluation Board to interface the MB86930 with the DRAM subsystem. The main objective of the paper is to show the simplicity of the external design requirements, while achieving high performance of three CPU cycle page mode access at 40MHz. ?
LatticeECP3 memory usage guide 2009-05-20
This technical application note discusses memory usage for the LatticeECP3 family of FPGA devices. It is intended to be used by design engineers as a guide to integrating the Embedded Block RAM (EBR)- and PFU-based memories for this device family in ispLEVER. ?
Interfacing the X24C44/45 NOVRAMs to the Motorola 6805 microcontroller using the SPI port 2003-04-30
This application note presents a code that demonstrates how the X24C44/45 serial NOVRAMs can be interfaced to Motorola 6805 microcontroller using the SPI port. ?


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