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EE Times Asia - total search?15?articles sort by date sort by relevance
Using ATM chipset in DSL architectures 2006-02-01
Learn the different traffic-management functions of DSL architectures for high-speed Internet access. ?
PCI-Based Centralized And Decentralized Systems 2001-07-02
This paper gives a performance analysis of the data transfer on the PCI bus between the local SDRAM and any other device sitting on the PCI bus. ?
Improving data bandwidth using 32-bit processors in embedded applications 2000-05-03
This paper describes how to integrate high-performance microprocessors and system controller functions for application-specific products, especially on cost-sensitive and space-limited products. ?
Green semiconductor packaging: Addressing the environmental concerns of the 21st century 2006-02-01
No development can proceed without closely examining the environmental impact of using a product and its compliance with global environmental regulations. ?
Centralized And Decentralized PCI Based Systems 2001-04-02
This paper gives a performance analysis of the data transfer on the PCI bus between the local SDRAM and any other device sitting on the PCI bus. ?
The lowdown on high-perf timing in board design 2013-12-23
Know the various scenarios facing board designers when working with high-performance timing. ?
NVMe paves the way for SSDs in the enterprise 2012-12-11
Scalable host controller interface for PCIe SSDs provides an optimised register interface, end-to-end data protection and performance across multiple cores. ?
Jitter concerns when selecting timing solutions 2015-07-10
Determining the effects of jitter on the system, as well as defining the jitter budgets for the various sub-systems are the keys to optimising system performance. ?
How to improve FPGA comms interface clock jitters 2014-10-16
Know how external phase locked loops can be used to resolve problems faced when dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes. ?
How to achieve 200-400GE network buffer speeds 2014-11-27
Know how a serial chip-to-chip protocol, with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate throughput bottlenecks at the processor/external DDR memory interface. ?
Grasp the significance of gesture interface 2013-05-02
When combined with other advanced user interface technologies, gestures can create a richer user experience that strives to understand the human language, thereby fueling the next wave of electronic innovation. ?
Determine acceptable jitter level in embedded design 2014-11-12
Learn about the nuances of clock jitter specifications, and know how to determine the acceptable level of jitter early on in the development cycle to prevent dire impact on end product release schedules. ?
Dealing with jitter vs power trade-off in clock trees 2015-09-03
Advanced clock buffers eliminate that trade-off between lower-jitter buffers with a power penalty you can't afford versus lower-power units with inferior jitter specifications. ?
Calibration of gain, timing errors in ADCs 2014-07-14
Here's a look at a novel background calibration method for gain and timing mismatch errors through low complexity digital signal processing algorithms. ?
Adapting a PCIe design to specific app needs 2013-07-16
With the appropriate mix of PCIe clock generators and buffers, embedded systems developers can address the unique requirements of various applications. ?


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