| Mentor CEO argues FPGAs will drive platforms
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2001-05-01 |
| This article describes how FPGA platforms will innovate designs and how engineers can make the most out of it. |
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Testing designs containing embedded blocks
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2000-05-01 |
| Deep-submicron processes enable increased complexity, which means that many of the embedded blocks cannot be tested using traditional methods. You must find new solutions to avoid risking product quality. |
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| Test takes new role in yield improvement
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2006-05-01 |
| New test methodologies focusing on identifying failure mechanisms provide a valuable feedback link to help you gauge success in product development. |
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| Significance of LED thermal characterisation
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2014-02-26 |
| Learn how improving the thermal characterisation of LEDs will help to spur on the LED lighting revolution. |
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| New DFM methods enable early yield prediction
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2006-09-18 |
| New DFM methodologies such as RRA and CAA, combined with traditional DRC and accurate fab yield impact data, enable designers to determine whether design modifications actually result in higher-yielding silicon. |
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| Meeting the challenges of co-design
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2000-03-01 |
| Even though the promise of co-design has not yet materialized, there is a decided benefit in easily transitioning among plausible architectures in order to perform high-level trade-off analysis. |
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| Long road ahead for analog synthesis
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2000-05-01 |
| It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital. |
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| IBIS 4.1 enhances signal-integrity modeling
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2005-09-16 |
| Find out the latest enhancements of IBIS 4.1 to keep signal-integrity modeling standards open and public |
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| Formal verification by equivalence checking in deep sub-micron designs
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2000-09-01 |
| Equivalence verification tools compare the logical behavior of two circuits while ensuring a consistent design flow. They aim to combine structural checking with handling of multi-million gate designs in a small memory footprint. |
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| Familiar faces help overseas EEs feel at home
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2001-01-01 |
| As more and more companies go overseas for new hires, engineers are stepping in, becoming mentors to minimize the newcomer's bewilderment. |
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| Design Issues And Verification Challenges For Home Networks
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2001-03-27 |
| This paper looks into some of the challenging questions and considerations when choosing the right processor for the Home Network application design. |
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| Address system-level design tasks
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2007-01-16 |
| The goal of a new system-level design methodology through ESL is to realize direct benefits in the design flow. Validating the system functional behavior as early as possible helps reduce iteration. |
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| Accelerate FPGA design success with early defect discovery
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2006-02-16 |
| Having better upfront visibility into possible defects in HW/SW interaction can prevent the need for FPGA respins. |
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| Trends to consider when choosing tools
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2007-12-17 |
| There are many factors to consider during PCB evaluation. Sylvia Teo of Mentor Graphics discusses how to address the challenges in PCB design and what factors must be considered when evaluating a PCB design tool. |
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| Team up to win the yield game in the nm era
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2008-03-03 |
| Designers and manufacturers are two sides of the same team, sharing a common goalyield. To win out, they need to align their strategies, their skills and their knowledge, and work together to overcome the challenges. That's the way the game is played in the nanometer era, says Anthony Nicoli of Mentor Graphics. |
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| What makes hardware emulation so compelling
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2015-11-23 |
| Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Utilising a memory management unit
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2014-02-25 |
| Learn about the workings of a memory management unit and its applications. |
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| Using DRC for SERDES PCB layouts
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2015-08-20 |
| In order to be sure that SERDES bus traces on a routed printed circuit board are error free, you may use an automated design rule checker, which makes such tasks easier. |
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| Use multi-core with multi-OS software architecture
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2013-10-14 |
| Here's a look at the architectural choices from the hardware capabilities to the software options, and how to make them efficient. |
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| Understanding multicore basics: AMP and SMP
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2014-06-27 |
| There are a variety of choices in terms of both hardware and software architecture, the selection of which is strongly dictated by the application. Now that multi-core embedded systems is on its way to becoming the standard, there are broadly two options to consider: Asymmetric Multi-Processing and Symmetric Multi-Processing. |
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| Understanding design compilation in hardware emulators
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2015-03-26 |
| Design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology utilised in the verification engine. |
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| Understanding data storage in NVM
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2014-12-18 |
| Using non-volatile random access memory in an embedded design is straightforward, but its functionality does need to be carefully accommodated as described in this article. |
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| Thwarting IoT security threats with ARM TrustZone
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2014-09-04 |
| Virtualisation can be leveraged to enable consolidation of connected devices, and ARM TrustZone can be utilised to tackle security threats to the Internet of Things. |
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| The ideal union of PAM and Ethernet
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2016-05-16 |
| Understand how various Ethernet speeds evolved through the utilisation of various pulse amplitude modulation (PAM) schemes. |
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| Targeting small delay defects
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2010-01-13 |
| To maintain the quality of test for the reasonable DPM levels, more and more test engineers are looking to target small delay defects with ATPG. |
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| Taking advantage of TSMC's 28HPC process
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2015-04-30 |
| Here are five areas where designers can take advantage of this new process with logic library technology to optimise the performance, power and area of their system on chips. |
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| Spot IGBT degradation through power cycling
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2015-09-17 |
| Here is a look at an experiment in which we conducted thermal transient tests from one steady-state to another to determine cause of failure for a small sample of IGBTs. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| SoCs likely to pose heading-off test problems
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2000-12-01 |
| This technology news article describes the problems and solutions test engineers should face when confronting SoC designs. |
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