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Formal Verification Tool news and hot articles

2009-10-30 Freescale, Synopsys extend verification tie-up
Freescale and Synopsys have teamed up to address verification metrics, including compute farm efficiency and engineer productivity.
2009-10-06 Analysis: TI fab deal is good for IC tool vendors
Equipment executives and analysts say that the TI fab deal isn't a blow to the equipment industry. Some suggested that it might even be a positive for gear suppliers.
2009-10-05 Identifying the most favored embedded tool
What is your favorite tool in the embedded world? Here's an interpretation of the Embedded Market Survey.
2009-10-05 Braving software-to-silicon verification challenges at 45nm
Software-to-silicon verification holds immense challenges at 45nm and beyond for system designers and tool vendors, with multiple paradigm shifts converging at the same time.
2009-08-28 MHI to build Li-ion battery verification plant
Mitsubishi announced plans to establish a commercial production verification plant in Nagasaki Prefecture.
2009-08-19 NI, SolidWorks co-develop mechatronics prototype tool
National Instruments and Dassault Systemes SolidWorks are working on a mechatronics tool for motion system design.
2009-08-10 Simulation tool goes online
Fairchild Semiconductor has released a Web-based simulation tool to help designers of portable applications to quickly and accurately assess the performance of advanced load switches in actual application circuits.
2009-07-22 Fab tool collaboration: Mission impossible?
Will the day come when rival fab tool vendors will throw out the rule book and collaborate with each other on new equipment R&D projects��just to help the industry keep pace on Moore's Law?
2009-07-15 Coaxial connector tailored for PCB verification
ITT Interconnect Solutions has unveiled an RF switching coaxial connector designed for antenna and PCB performance verification.
2009-07-07 Signal generators tailored for RF design verification
PXI modular test platform welcomes new family members with the arrival of two RF signal generators.
2009-06-25 Intel: Fab tool market savior?
Intel Corp. continues to fund technologies and procure fab-equipment, but behind the scenes, the company is investing in some companies and brokering deals for others, reportedly including ASM International NV and NuFlare Technology Inc., sources said.
2009-06-23 Asynchronous synthesis tool uses standard languages
Tiempo AS will demonstrate what it touts as the first synthesis tool for asynchronous logic that operates from standard design languages at the Design Automation Conference.
2008-09-04 Tool suite upgrade touts faster fault detection
LDRA, the leading provider of automated software verification, source code analysis, and test tools, has launched the LDRA tool suite v7.7
2007-10-31 Startup rolls automated device driver generator
Vayavya Labs is launching an automated device driver generator framework that the company claims will bring discipline through its formal language-based approach
2007-06-14 Simulink design suite adds formal methods
Adding formal design methods to its widely used Simulink model-based design suite, The Mathworks Inc. has introduced the Simulink Design Verifier, which generates tests and proves properties for models from the company's Simulink simulation platform and Stateflow design and simulation tool
2007-04-25 Device-native verification tool rolls for FPGAs
Startup GateRocket has rolled out a device-native FPGA verification solution that includes hardware and software
2007-02-26 IAR Systems upgrades visualSTATE design tool
IAR Systems has launched the latest version of its state machine embedded design and verification tool��visualSTATE 5.4��featuring a tighter integration to IAR Embedded Workbench
2007-02-01 Cadence deploys CPF in low-power design flow
Cadence Design Systems has added the Common Power Format (CPF) to its existing logic design, verification and implementation tools
2006-11-08 Equivalence checker eyes clock gating
The sequential equivalence checker that Calypto Design Systems will release soon promises to automate the verification of clock-gating circuitry
2006-09-01 EDA startup offers free verification planning tool
Verification-focused EDA startup Jasper Design Automation is making available a free tool for tracking the progress of verification plans
2006-07-26 Formal verification tool promises finer control
Averant released the next generation of its formal verification tool, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs
2005-09-28 Sequence Design introduces 'formal' power grid verification
Looking to build on its reputation as an established provider of IC power management technology, Sequence Design rolled out a new product focused on another thermal issue��IC power grid integrity.
2005-05-04 Cadence formal analysis claims ease of use
Cadence Design Systems is introducing this week Incisive Formal Verifier, a tool that aims to make it easy for IC designers verify assertions in RTL code
2005-03-21 Formal tool able to verify false paths
Real Intent's new software timing-exception prover promises to save designers from a lengthy manual review cycle.
2005-01-27 Synplicity upgrades FPGA synthesis
Synplicity released a new version of its Synplify Pro FPGA synthesis tool boasting major run time and quality of results improvements
2005-01-20 Cadence releases design constraint checker
Cadence released a new formal analysis tool that generates, analyzes and validates the quality of design constraints designers use to run synthesis, timing analysis and place-and-route tools
2008-08-21 Mentor, Altera propel avionics design with DO-254 IP
Altera Corp. and Mentor Graphics Corp. announced the companies are working together to develop tools and methodologies for use in creating DO-254-certifiable intellectual property that targets Altera's FPGA and HardCopy ASIC solutions.
2008-08-01 Developing a green product development strategy
One of the most difficult steps in the initiation of a green product development strategy is where to get started. The green knowledge base for product development is widely distributed and not readily available within the organization, in the design or process teams.
2008-02-26 Rhines on EDA: End 'endless verification
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification
2007-09-17 Formal verification fetches better results
Complete formal verification is not a silver bullet for all functional verification tasks. But for a broad range of digital modules and IP, it delivers far superior results in terms of verification quality, effort and costs
2007-09-17 Optimal use of assertions in verification
Assertions provide an efficient way of improving overall design cycle productivity by cutting verification time. Here are some tips in the optimal use of assertions in verification
2007-06-18 The intricate dance of cutting power consumption
Key players in the industry are collaborating to deliver low-power solutions that bring more automated EDA tools, smarter IP, standard formats and more power-stingy processes together into true end-to-end solutions. EDA and IP companies have worked within the Accellera standards organization to develop the Unified Power Format (UPF).
2007-06-18 Define your verification plan with SystemVerilog
The adoption of constrained random testbenches, functional coverage and assertions fits seamlessly with embracing SystemVerilog. The value of these technologies is enhanced with an evolution of the verification planning process from simple test plans to VPA-driven verification plans
2007-04-16 Equivalence checker supports FPGA optimizations
Startup OneSpin Solutions GmbH has introduced a solution that makes FPGA equivalence checking practical by supporting those optimizations.
2007-03-19 Plan your verification process with SystemVerilog
The best way for the verification team to match the automatic tests with their corresponding design features is via functional coverage metrics
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools
2006-09-18 Cadence CTO mulls over CAD architecture, EDA
Cadence Design Systems Inc. senior VP and CTO, Ted Vucurevich, sat down recently with EE Times' Richard Goering and discussed developments ranging from new CAD architectures to EDA tools for nanotechnology-based systems like labs-on-a-chip.
2006-09-18 Averant dives deep into formal verification
Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification
2006-09-18 EDA rivals spar over power issues
Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working toward that objective, amid profound disagreements over how to get there.
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2006-06-01 Breaking the verification barrier
Startup OneSpin Solutions believes it has technology that will usher in a new era of IC formal verification. But if this company is successful, the real breakthrough may be one of bringing internal technology from a large integrated device manufacturer into a global, commercial EDA market
2006-05-01 Novas tool lets designer see data from debugging
This new type of tool set should help IC designers gain visibility into the signal values they really want to see
2006-04-17 Vendors warm to SystemVerilog
Despite Synopsys' skepticism, synthesis vendors appear strongly supportive of a proposed standard SystemVerilog synthesis subset.
2006-03-30 Sequans used Synopsys' tools in WiMAX/WiBro chip development
Synopsys announced that Sequans Communications has adopted key components of the Discovery Verification Platform and standardized on the Synopsys VCS comprehensive RTL verification solution
2006-03-22 Synopsys claims first complete SystemVerilog flow
Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products
2006-02-01 Language standards from IEEE open choices
Once seen as competitors, SystemC and SystemVerilog languages appear to be settling into largely complementary niches.
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2005-09-01 Leaky chips test designers' skills
To achieve longer battery life in portable products, the entire IC design chain must chip in and tackle leakage.
2005-07-29 Synopsys test methodologies verify SLE's chip developments
Synopsys Inc. announced that its VCS comprehensive RTL verification solution and Vera testbench automation tool have been adopted by ASIC design services provider Silicon Logic Engineering (SLE) to accelerate its chip development process
2005-07-01 Analog EDA firm tackles PLL noise
Berkeley's PLL noise analyzer promises to shrink time-to-volume for discrete analog/RF chips and SoCs containing analog blocks.
2005-06-14 Emerging DFM, verification technologies most exciting, CTOs say
Emerging technologies for design for manufacturing (DFM) and verification are the most exciting developments in the design realm, concluded a panel of chief technology officers convened here Monday (June 13) at the Design Automation Conference (DAC
2005-05-02 Addressing EDA's malaise
Today, when you hear the word EDA, what comes to mind? Failed companies. Flat revenues. Endless lawsuits. Marketing hype. Depressed market values.
2005-04-01 Is EDA's world too provincial?
If EDA wants to come out of its current stagnation, it may be time to broaden the focus.
2005-03-10 IBM EDA tools emerge from Europe's Prosyd project
One year after the launch of the Prosyd collaborative research project between IBM Corp., Infineon Technologies AG and STMicroelectronics NV with about 4 million euros (about $5.3 million) of European tax payers' money, the project has helped IBM produce chip design verification tools
2005-01-31 Back to the language roots
Although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL.
2005-01-21 Startup claims to optimize IC layouts for yield
Even the best chip layouts need some help to maximize IC yields, according to startup Nannor Technologies Inc., which is quietly preparing a layout optimization tool
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