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Verilog news and hot articles

2007-08-17 Xilinx tool eases FPGA to PCB interface
PlanAhead 9.2 from Xilinx eases managing the interface between the designer's target FPGA and the PCB with the ability to import and export I/O port information through VHDL or Verilog headers
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms
2006-11-01 HDL Coder offers shortcut to IC design
The Mathworks Inc. offers the Simulink HDL Coder, which automatically generates synthesizable Verilog and VHDL from Simulink models and Stateflow diagrams
2006-10-17 Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software.
2006-03-31 Aldec offers 90-day free access to Riviera Verilog simulator
Aldec announced full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.
2005-12-08 Tool ARMs for SoC validation
Carbon Design Systems' SOC-VSP extends ARM's RealView SoC Designer to import "Carbonized" VHDL or Verilog RTL models
2005-07-01 Tips for compiling software to gates
VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages
2005-06-13 Celoxica ESL design suite upgrade expands speed, size limits
Celoxica's DK Design Suite introduces VHDL and Verilog optimizations that work with Design Compiler from Synopsys Inc
2005-02-01 Bluespec synthesizes SystemVerilog verification assertions
The startup has announced its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL code
2005-01-31 Back to the language roots
Although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL
2005-01-25 Tharas announces support for Verilog 4-state logic simulation
Tharas Systems announced its support for Verilog 4-state logic simulation in its Hammer 100
2004-11-22 Toshiba adopts Mentor ADVance MS tool in LSI designs
Mentor Graphics Corp. revealed that Toshiba Corp. has adopted its analog/mixed-signal HDL language, Verilog-AMS, for the design and verification of complex analog and mixed-signal LSI (large scale integration) designs
2004-10-13 Mentor tool suite offers complete implementation of Verilog 2001
Mentor disclosed that they have made key enhancements in its newly-released Precision Synthesis tool suite.
2004-08-12 Synthesis suite targets unconventional designs
FTL's Merlin is a tool suite that includes behavioral synthesis from VHDL or SystemVerilog; analog synthesis from VHDL-AMS or Verilog-AMS; and analysis and simulation
2004-07-16 Consultant creates low-end mixed-signal simulator
uSysIntegral is going into beta testing with XSpiceHDL, which links the XSpice circuit simulator from the Georgia Technical Research Institute to commercial Verilog simulators
2004-06-29 IEEE unifies Verilog standards efforts
Putting to rest fears of a Verilog language schism, the IEEE has decided to form a single working group that will encompass both SystemVerilog and the further evolution of the IEEE 1364 Verilog language standard
2004-06-16 The C programmer's guide to Verilog
This will look at how to implement PWM in software and then turn the design into a logic block that can run from an FPGA and be controlled via software using a memory-mapped I/O interface.
2004-06-08 AccelChip partners with Leopard Logic, ChipX
EDA startup AccelChip Inc., a provider of tools for synthesizable Verilog and VHDL code, has signed separate partnership deals with structured ASIC vendor ChipX and configurable logic vendor Leopard Logic
2004-06-03 Cadence, CoWare partner on ESL-to-RTL verification
Last September's partnership between CoWare Inc. and Cadence Design Systems Inc. has yielded its first fruits, as the companies are introducing a new co-developed flow they claim will allow users of CoWare's ConvergenSC SystemC-based prototyping system to "seamlessly" transfer models built in SystemC and Verilog to Cadence's Incisive verification platform
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications
2004-05-13 Tharas spins new accelerator box
Tharas' new version of its hardware accelerator compiles Verilog, VHDL or mixed-language designs at rates of 20 to 50 million register-transfer-level equivalent gates per hour
2004-04-12 SynaptiCAD joins graphical debugging market
Offering a graphical debugging system that can control Verilog, VHDL, and C++ simulators, SynaptiCAD has announced BugHunter Pro
2004-03-23 Verilog reader/writer boosts OpenAccess reach
Plugging a major gap that has made it difficult for chip designers and EDA vendors to embrace the OpenAccess database, Hewlett-Packard, and Cadence Design Systems have donated a Verilog reader/writer to the OpenAccess Coalition
2004-03-15 Engineer offers free obfuscator, layout scanner
Inspired by a user request in the E-Mail Synopsys Users Group (ESNUG), an engineer working in Singapore developed a Verilog source-code obfuscator, a GDSII layout viewer, and a layout scanner that calculates wire length
2004-03-05 Silvaco offers open-source Verilog-A models
Silvaco International is offering nine Verilog-A device models for free download under open-source distribution
2004-01-16 ...Obfuscators' render Verilog, VHDL unreadable
Providing a new approach to IP protection, software engineering firm Semantic Designs has released production-quality "obfuscators" for Verilog 2001 and VHDL
2004-01-08 Agilent adds Verilog-A support
Claiming a significant advantage over proprietary models, Agilent Technologies has introduced Verilog-A support for its RF Design Environment
2004-01-05 EDA startup offers graphical Verilog tool
Aiming to simplify HDL code development and documentation, Orion Consulting Inc. has rolled out Visual RTL.
2004-01-01 0-In assertion compiler is multilingual
0-In Design Automation announced a compiler that reads assertions in multiple formats and outputs synthesizable Verilog
2003-10-10 Silvaco buys EDA pioneer Simucad
Aiming for the mixed-signal IC design market, Silvaco Int. has purchased the assets of Verilog simulation provider Simucad Inc
2003-10-09 IEEE approves ALF, synthesis standards
Paving the way for greater library and EDA tool interoperability, IEEE has approved Accellera's Advanced Library Format and Verilog and VHDL synthesis subsets
2003-09-09 Verilog won't diverge, user reps pledge
Although the IEEE and the Accellera standards organization appear to be heading in different directions with next-gen Verilog, IEEE 1364 Working Group and Accellera's SystemVerilog committee members said they won't allow incompatible standards to emerge
2003-08-01 Coexistence in a multilingual design world
Even while they are commonly depicted as opposites, it is clear that Verilog and SystemC have complementary roles in moving designs from specification to implementation
2003-07-28 Agilent taps startup's Verilog-A compiler
Adding behavioral modeling to its analog design tool suites, Agilent announced an agreement to integrate Verilog-A modeling technology from Tiburon-DA
2003-06-02 Ready for the Verilog split
Richard Goering agrees with Cadence that incompatibility between System Verilog 3.1 and IEEE 1364 standard verilog is possible
2003-05-29 Verilog simulator supports 64-bit Linux
Claiming a new level of performance, Fintronic USA has announced that its Super FinSim Verilog simulator now runs on 64-bit Linux workstations
2003-05-02 Speeding up simulation
The paper presented by Rajesh Bawankule at the recent DVCon can help engineers to speed up verilog without spending a single penny
2003-04-14 Tenison Verilog solution selected by Seaway
Tenison EDA announced that fabless semicon company Seaway Networks Inc. has adopted its Verilog/VHDL to C/C++ modeling solution
2003-04-09 Cadence decries incompatible Verilog versions
The EDA industry is risking "disaster" with two separate and incompatible versions of Verilog unless the Accellera standards organization quickly hands over SystemVerilog 3.1 to the IEEE, according to Cadence Design Systems Inc
2003-03-12 Spreadsheet tool generates HDL interfaces
The MatrixHDL tool allows users to enter interface descriptions and automatically generate VHDL or Verilog
2003-03-03 Synopsys upgrades VCS and Vera
The company has announced upgrades to its VCS 7.0 Verilog simulator and Vera testbench automation tool
2003-01-14 Open-source tool converts HDL to HTML
An open-source tool from Millogic converts Verilog or VHDL code to HTML for Web browser viewing
2002-10-18 Open-source tool links Verilog with TCL
An open-source tool developed by Acculent Corp. promises to convert TCL scripts into Verilog code
2002-10-01 'Religious' wars abound
Should resets be synchronous or asynchronous? Should synthesis handle buffer insertion? Should OpenVera assertions be added to System Verilog? All these questions have provoked controversies in recent weeks, the first two in E-Mail Synopsys Users' Group (ESNUG) postings and at our EEdesign site
2002-09-23 Startup to offer online Verilog training sessions
Mindbrook Inc. will initiate an online Verilog training program that offers software design collaboration in 1H of 2003
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